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<div class="title">xhdmiphy1.c File Reference</div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>Contains a minimal set of functions for the <a class="el" href="struct_x_hdmiphy1.html" title="The XHdmiphy1 driver instance data. ">XHdmiphy1</a> driver that allow access to all of the Video PHY core's functionality. </p>
<p>See <a class="el" href="xhdmiphy1_8h.html">xhdmiphy1.h</a> for a detailed description of the driver.</p>
<dl class="section note"><dt>Note</dt><dd>None.</dd></dl>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
</p>
<hr/>
<p>
           dd/mm/yy
</p>
<hr/>
<p>
1.0   gm   10/12/18 Initial release.
1.1   ku   17/05/20 Adding uniquification to avoid clash with vphy
1.1   ku   27/07/20 Removed GTHE3 related code
1.2   ssh  22/07/22 Added multi gt support and updated the frl and
                       dru clk freq to 200MHz for -1 GTHE4 and GTYE4 device
1.3   ssh  18/10/22 Updated the extended txdiffctrl mask and added
                       support for NI-DRU diabled case
1.4   ssh  10/09/24 Added DPLL clock primitive support for Versal
</pre><p>See <a class="el" href="xhdmiphy1_8h.html">xhdmiphy1.h</a> for a detailed description of the driver.</p>
<dl class="section note"><dt>Note</dt><dd>None.</dd></dl>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
</p>
<hr/>
<p>
           dd/mm/yy
</p>
<hr/>
<p>
1.0   gm   10/12/18 Initial release.
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gac17db2af38544c85cb299d147fcdac16"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">XHdmiphy1_CfgInitialize</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="struct_x_hdmiphy1___config.html">XHdmiphy1_Config</a> *ConfigPtr, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:gac17db2af38544c85cb299d147fcdac16"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function retrieves the configuration for this Video PHY instance and fills in the InstancePtr-&gt;Config structure.  <a href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">More...</a><br/></td></tr>
<tr class="separator:gac17db2af38544c85cb299d147fcdac16"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga82f13f4133bdf9ab03d845c8462dc091"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga82f13f4133bdf9ab03d845c8462dc091">XHdmiphy1_PllInitialize</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, <a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> QpllRefClkSel, <a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> CpllRefClkSel, <a class="el" href="group__xhdmiphy1.html#gae8559ee2ca7c404467a72f4653a5d4f5">XHdmiphy1_PllType</a> TxPllSelect, <a class="el" href="group__xhdmiphy1.html#gae8559ee2ca7c404467a72f4653a5d4f5">XHdmiphy1_PllType</a> RxPllSelect)</td></tr>
<tr class="memdesc:ga82f13f4133bdf9ab03d845c8462dc091"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will initialize the PLL selection for a given channel.  <a href="group__xhdmiphy1.html#ga82f13f4133bdf9ab03d845c8462dc091">More...</a><br/></td></tr>
<tr class="separator:ga82f13f4133bdf9ab03d845c8462dc091"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabe478d42590c0365f3e2feb3933321ec"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gabe478d42590c0365f3e2feb3933321ec">XHdmiphy1_WaitUs</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u32 MicroSeconds)</td></tr>
<tr class="memdesc:gabe478d42590c0365f3e2feb3933321ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the delay/sleep function for the <a class="el" href="struct_x_hdmiphy1.html" title="The XHdmiphy1 driver instance data. ">XHdmiphy1</a> driver.  <a href="group__xhdmiphy1.html#gabe478d42590c0365f3e2feb3933321ec">More...</a><br/></td></tr>
<tr class="separator:gabe478d42590c0365f3e2feb3933321ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6a4e05c5b6141f00bdfa2ae1f30b15a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaf6a4e05c5b6141f00bdfa2ae1f30b15a">XHdmiphy1_GetVersion</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaf6a4e05c5b6141f00bdfa2ae1f30b15a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will obtian the IP version.  <a href="group__xhdmiphy1.html#gaf6a4e05c5b6141f00bdfa2ae1f30b15a">More...</a><br/></td></tr>
<tr class="separator:gaf6a4e05c5b6141f00bdfa2ae1f30b15a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga71a574c5aedf401c9b7c59a173822f8f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga71a574c5aedf401c9b7c59a173822f8f">XHdmiphy1_CfgLineRate</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u64 LineRateHz)</td></tr>
<tr class="memdesc:ga71a574c5aedf401c9b7c59a173822f8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the channel's line rate.  <a href="group__xhdmiphy1.html#ga71a574c5aedf401c9b7c59a173822f8f">More...</a><br/></td></tr>
<tr class="separator:ga71a574c5aedf401c9b7c59a173822f8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97e1d4070dafe5a73d9bf60621382c98"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gae8559ee2ca7c404467a72f4653a5d4f5">XHdmiphy1_PllType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga97e1d4070dafe5a73d9bf60621382c98">XHdmiphy1_GetPllType</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:ga97e1d4070dafe5a73d9bf60621382c98"><td class="mdescLeft">&#160;</td><td class="mdescRight">Obtain the channel's PLL reference clock selection.  <a href="group__xhdmiphy1.html#ga97e1d4070dafe5a73d9bf60621382c98">More...</a><br/></td></tr>
<tr class="separator:ga97e1d4070dafe5a73d9bf60621382c98"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga31263f99c22623f852ea864fba080232"><td class="memItemLeft" align="right" valign="top">u64&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga31263f99c22623f852ea864fba080232">XHdmiphy1_GetLineRateHz</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:ga31263f99c22623f852ea864fba080232"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will return the line rate in Hz for a given channel / quad.  <a href="group__xhdmiphy1.html#ga31263f99c22623f852ea864fba080232">More...</a><br/></td></tr>
<tr class="separator:ga31263f99c22623f852ea864fba080232"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7f1f22be7f2029c396c015e322475790"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga7f1f22be7f2029c396c015e322475790">XHdmiphy1_ResetGtPll</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, u8 Hold)</td></tr>
<tr class="memdesc:ga7f1f22be7f2029c396c015e322475790"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will reset the GT's PLL logic.  <a href="group__xhdmiphy1.html#ga7f1f22be7f2029c396c015e322475790">More...</a><br/></td></tr>
<tr class="separator:ga7f1f22be7f2029c396c015e322475790"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga117b1b06a6044a0574731e960e8e304a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga117b1b06a6044a0574731e960e8e304a">XHdmiphy1_ResetGtTxRx</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, u8 Hold)</td></tr>
<tr class="memdesc:ga117b1b06a6044a0574731e960e8e304a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will reset the GT's TX/RX logic.  <a href="group__xhdmiphy1.html#ga117b1b06a6044a0574731e960e8e304a">More...</a><br/></td></tr>
<tr class="separator:ga117b1b06a6044a0574731e960e8e304a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga615fe597062a12b286153f2ee8007e91"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga615fe597062a12b286153f2ee8007e91">XHdmiphy1_SetPolarity</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, u8 Polarity)</td></tr>
<tr class="memdesc:ga615fe597062a12b286153f2ee8007e91"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set/clear the TX/RX polarity bit.  <a href="group__xhdmiphy1.html#ga615fe597062a12b286153f2ee8007e91">More...</a><br/></td></tr>
<tr class="separator:ga615fe597062a12b286153f2ee8007e91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga041ec28c400f1b4cb662d9670e0feff3"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga041ec28c400f1b4cb662d9670e0feff3">XHdmiphy1_SetPrbsSel</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, <a class="el" href="group__xhdmiphy1.html#ga3532b332baefc7e9454c8d485aedb4c9">XHdmiphy1_PrbsPattern</a> Pattern)</td></tr>
<tr class="memdesc:ga041ec28c400f1b4cb662d9670e0feff3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the TX/RXPRBSEL of the GT.  <a href="group__xhdmiphy1.html#ga041ec28c400f1b4cb662d9670e0feff3">More...</a><br/></td></tr>
<tr class="separator:ga041ec28c400f1b4cb662d9670e0feff3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae474ac8f1f2997229ec25e7584a4b827"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gae474ac8f1f2997229ec25e7584a4b827">XHdmiphy1_TxPrbsForceError</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 ForceErr)</td></tr>
<tr class="memdesc:gae474ac8f1f2997229ec25e7584a4b827"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the TX/RXPRBSEL of the GT.  <a href="group__xhdmiphy1.html#gae474ac8f1f2997229ec25e7584a4b827">More...</a><br/></td></tr>
<tr class="separator:gae474ac8f1f2997229ec25e7584a4b827"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa01b2c0214336ba205fcac3c8fd7675d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaa01b2c0214336ba205fcac3c8fd7675d">XHdmiphy1_SetTxVoltageSwing</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Vs)</td></tr>
<tr class="memdesc:gaa01b2c0214336ba205fcac3c8fd7675d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the TX voltage swing value for a given channel.  <a href="group__xhdmiphy1.html#gaa01b2c0214336ba205fcac3c8fd7675d">More...</a><br/></td></tr>
<tr class="separator:gaa01b2c0214336ba205fcac3c8fd7675d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9dd0d271c9be7416e55adc535257cea"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gad9dd0d271c9be7416e55adc535257cea">XHdmiphy1_SetTxPreEmphasis</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Pe)</td></tr>
<tr class="memdesc:gad9dd0d271c9be7416e55adc535257cea"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the TX pre-emphasis value for a given channel.  <a href="group__xhdmiphy1.html#gad9dd0d271c9be7416e55adc535257cea">More...</a><br/></td></tr>
<tr class="separator:gad9dd0d271c9be7416e55adc535257cea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga755a209f0abe848a3508017f83ad4c62"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga755a209f0abe848a3508017f83ad4c62">XHdmiphy1_SetTxPostCursor</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Pc)</td></tr>
<tr class="memdesc:ga755a209f0abe848a3508017f83ad4c62"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the TX post-curosr value for a given channel.  <a href="group__xhdmiphy1.html#ga755a209f0abe848a3508017f83ad4c62">More...</a><br/></td></tr>
<tr class="separator:ga755a209f0abe848a3508017f83ad4c62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga704b9c7161c4ac92beaa07113caaa36c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga704b9c7161c4ac92beaa07113caaa36c">XHdmiphy1_SetRxLpm</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, u8 Enable)</td></tr>
<tr class="memdesc:ga704b9c7161c4ac92beaa07113caaa36c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will enable or disable the LPM logic in the Video PHY core.  <a href="group__xhdmiphy1.html#ga704b9c7161c4ac92beaa07113caaa36c">More...</a><br/></td></tr>
<tr class="separator:ga704b9c7161c4ac92beaa07113caaa36c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga632197e5f773491cdf96f076e7112e0f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga632197e5f773491cdf96f076e7112e0f">XHdmiphy1_DrpWr</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u16 Addr, u16 Val)</td></tr>
<tr class="memdesc:ga632197e5f773491cdf96f076e7112e0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will initiate a write DRP transaction.  <a href="group__xhdmiphy1.html#ga632197e5f773491cdf96f076e7112e0f">More...</a><br/></td></tr>
<tr class="separator:ga632197e5f773491cdf96f076e7112e0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga55c5c6061828e1f986b64d4c0ae9a57b"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga55c5c6061828e1f986b64d4c0ae9a57b">XHdmiphy1_DrpRd</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u16 Addr, u16 *RetVal)</td></tr>
<tr class="memdesc:ga55c5c6061828e1f986b64d4c0ae9a57b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will initiate a read DRP transaction.  <a href="group__xhdmiphy1.html#ga55c5c6061828e1f986b64d4c0ae9a57b">More...</a><br/></td></tr>
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<tr class="memitem:ga13859cf616b98f6d37336128b9f3f21a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga13859cf616b98f6d37336128b9f3f21a">XHdmiphy1_MmcmPowerDown</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Hold)</td></tr>
<tr class="memdesc:ga13859cf616b98f6d37336128b9f3f21a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will power down the mixed-mode clock manager (MMCM) core.  <a href="group__xhdmiphy1.html#ga13859cf616b98f6d37336128b9f3f21a">More...</a><br/></td></tr>
<tr class="separator:ga13859cf616b98f6d37336128b9f3f21a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5dc7ec503e2e78570719440c12773984"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga5dc7ec503e2e78570719440c12773984">XHdmiphy1_MmcmStart</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:ga5dc7ec503e2e78570719440c12773984"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will start the mixed-mode clock manager (MMCM) core.  <a href="group__xhdmiphy1.html#ga5dc7ec503e2e78570719440c12773984">More...</a><br/></td></tr>
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<tr class="memitem:ga57aac6b723825d9999dc5419d067bda3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga57aac6b723825d9999dc5419d067bda3">XHdmiphy1_IBufDsEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Enable)</td></tr>
<tr class="memdesc:ga57aac6b723825d9999dc5419d067bda3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the TX or RX IBUFDS peripheral.  <a href="group__xhdmiphy1.html#ga57aac6b723825d9999dc5419d067bda3">More...</a><br/></td></tr>
<tr class="separator:ga57aac6b723825d9999dc5419d067bda3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab511031505e9679f2bd243d68eb725f4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gab511031505e9679f2bd243d68eb725f4">XHdmiphy1_Clkout1OBufTdsEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, XHdmiphy1_DirectionType Dir, u8 Enable)</td></tr>
<tr class="memdesc:gab511031505e9679f2bd243d68eb725f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the TX or RX CLKOUT1 OBUFTDS peripheral.  <a href="group__xhdmiphy1.html#gab511031505e9679f2bd243d68eb725f4">More...</a><br/></td></tr>
<tr class="separator:gab511031505e9679f2bd243d68eb725f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90147f575dee01a888964ba10cdf4f73"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga90147f575dee01a888964ba10cdf4f73">XHdmiphy1_SetErrorCallback</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, void *CallbackFunc, void *CallbackRef)</td></tr>
<tr class="memdesc:ga90147f575dee01a888964ba10cdf4f73"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function installs a callback function for the HDMIPHY error conditions.  <a href="group__xhdmiphy1.html#ga90147f575dee01a888964ba10cdf4f73">More...</a><br/></td></tr>
<tr class="separator:ga90147f575dee01a888964ba10cdf4f73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7efb70724bc3a6fa0d3bd6c9d7d22de4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga7efb70724bc3a6fa0d3bd6c9d7d22de4">XHdmiphy1_SetLogCallback</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u64 *CallbackFunc, void *CallbackRef)</td></tr>
<tr class="memdesc:ga7efb70724bc3a6fa0d3bd6c9d7d22de4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function installs an asynchronous callback function for the LogWrite API:  <a href="group__xhdmiphy1.html#ga7efb70724bc3a6fa0d3bd6c9d7d22de4">More...</a><br/></td></tr>
<tr class="separator:ga7efb70724bc3a6fa0d3bd6c9d7d22de4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8dc19df05e15d413e62ff62d2c22c023"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga8dc19df05e15d413e62ff62d2c22c023">XHdmiphy1_RegisterDebug</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga8dc19df05e15d413e62ff62d2c22c023"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints out Video PHY register and GT Channel and Common DRP register contents.  <a href="group__xhdmiphy1.html#ga8dc19df05e15d413e62ff62d2c22c023">More...</a><br/></td></tr>
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